The NCG (Network Clock Generator) is used in the Hicom 340.2, 370.1, 370.3, 380.3 and 390.3 configurations. It can generate the system clock independently or synchronize with external reference clock suppliers, such as the TMX21, the TMD, the T1 board (USA) and the DIUxx.
If required, two central clock supply units can be used in duplex mode. The clock is supplied by the active NCG half (master). If a clock failure occurs, the master/slave status is reversed almost immediately, i.e. before a possible clock phase difference can affect the system periphery.
The central clock generator derives its system clock frequencies from the external reference clock suppliers; it attains the same frequency stability as the reference clock frequency. The board contains a monitoring circuit for detecting a clock failure in the quartz oscillator VCXO as well as watchdog timeouts. The firmware supervises the master/slave switchover, detects clock failures of the VCXO and monitors the ready line to the DP, the RAM and the EPROM.